The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2023

Filed:

Mar. 30, 2020
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Xinmin Yu, San Diego, CA (US);

Lai Kan Leung, San Marcos, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/02 (2006.01); G09G 5/00 (2006.01); H01Q 3/38 (2006.01); H03H 11/16 (2006.01); H03F 3/45 (2006.01); H03F 3/68 (2006.01); H01Q 21/22 (2006.01);
U.S. Cl.
CPC ...
H01Q 3/38 (2013.01); G09G 5/006 (2013.01); H01Q 21/22 (2013.01); H03F 1/0211 (2013.01); H03F 3/45179 (2013.01); H03F 3/68 (2013.01); H03H 11/16 (2013.01); G09G 2310/0254 (2013.01); G09G 2370/08 (2013.01); H03F 2200/294 (2013.01); H03F 2200/451 (2013.01); H03F 2203/45294 (2013.01); H03F 2203/45296 (2013.01); H03F 2203/45352 (2013.01);
Abstract

An apparatus is disclosed for bidirectional amplification with phase-shifting. In example implementations, an apparatus includes a phase shifter with a bidirectional amplifier. The bidirectional amplifier includes a first transistor coupled between a first plus node and a second minus node, a second transistor coupled between a first minus node and a second plus node, a third transistor coupled between the first plus node and the second minus node, and a fourth transistor coupled between the first minus node and the second plus node. The bidirectional amplifier also includes a fifth transistor coupled between the first plus node and the second plus node, a sixth transistor coupled between the first minus node and the second minus node, a seventh transistor coupled between the first plus node and the second plus node, and an eighth transistor coupled between the first minus node and the second minus node.


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