The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2023

Filed:

Jun. 26, 2020
Applicants:

Shanghai Tianma Micro-electronics Co., Ltd., Shanghai, CN;

Shanghai Avic Opto Electronics Co.,ltd., Shanghai, CN;

Inventors:

Xuhui Peng, Shanghai, CN;

Kerui Xi, Shanghai, CN;

Tingting Cui, Shanghai, CN;

Feng Qin, Shanghai, CN;

Jie Zhang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4853 (2013.01); H01L 21/486 (2013.01); H01L 21/4896 (2013.01); H01L 21/561 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 24/81 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 2924/37001 (2013.01);
Abstract

A semiconductor package and a method of forming the semiconductor package are provided. The method includes providing a first substrate, forming a wiring structure containing at least two first wiring layers, disposing a first insulating layer between adjacent two first wiring layers, and patterning the first insulating layer to form a plurality of first through-holes. The adjacent two first wiring layers are electrically connected to each other through the plurality of first through-holes. The method also includes providing at least one semiconductor element each including a plurality of pins. In addition, the method includes disposing the plurality of pins of the each semiconductor element on a side of the wiring structure away from the first substrate. Further, the method includes encapsulating the at least one semiconductor element, and placing a ball on a side of the wiring structure away from the at least one semiconductor element.


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