The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2023

Filed:

Jun. 02, 2021
Applicant:

Realtek Semiconductor Corp., Hsinchu, TW;

Inventors:

Zhi-Qiang Yang, Hsinchu, TW;

Jia-Jia Cai, Hsinchu, TW;

Bin Chen, Hsinchu, TW;

Dong Qiu, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G11C 29/52 (2013.01);
Abstract

A verifying method for an error checking and correcting (ECC) circuit of a static random-access memory (SRAM) is provided. The SRAM comprises a storage unit, an ECC circuit and a checking circuit. The ECC circuit receives an original data and an output first data. The checking circuit obtains a second data according to an error-injecting mask. The checking circuit performs a bit operation on the first data and the second data to obtain a third data. The checking circuit writes the third data into a test target area of the storage unit and the written data as a fourth data. The checking circuit reads the fourth data from the test target area. The ECC circuit obtains a fifth data and an error message according to the fourth data. The checking circuit obtains the bit error detection result according to the error message and the second data.


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