The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2023

Filed:

Feb. 26, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Masaomi Teranishi, Yokohama Kanagawa, JP;

Kentaro Inomata, Fujisawa Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/122 (2016.01); G06F 12/123 (2016.01); G06F 12/1027 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0647 (2013.01); G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G06F 12/1027 (2013.01); G06F 12/122 (2013.01); G06F 12/124 (2013.01); G06F 2212/657 (2013.01);
Abstract

According to one embodiment, a memory system includes a non-volatile memory array with a plurality of memory cells. Each memory cell is a multilevel cell to which multibit data can be written. The non-volatile memory array includes a first storage region in which the multibit data of a first bit level is written and a second storage region in which data of a second bit level less than the first bit level is written. A memory controller is configured to move pieces of data from the first storage region to the second storage region based on the number of data read requests for the pieces of data received over a period of time or on external information received from a host device that sends read requests.


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