The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2023

Filed:

Feb. 06, 2021
Applicant:

Skyechip Sdn Bhd, Bayan Lepas Pulau Pinang, MY;

Inventors:

Chee Hak Teh, Bayan Lepas Pulau Pinang, MY;

Yu Ying Ong, Bayan Lepas Pulau Pinang, MY;

Wong Ging Yeon Mark, Bayan Lepas Pulau Pinang, MY;

Tat Hin Tan, Bayan Lepas Pulau Pinang, MY;

Soong Khim Chew, Bayan Lepas Pulau Pinang, MY;

Assignee:

SKYECHIP SDN BHD, Bayan Lepas Pulau Pinang, MY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01); H03L 7/099 (2006.01); H03L 7/14 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0996 (2013.01); H03L 7/143 (2013.01);
Abstract

A device and method of clock synchronization for external memory interface. The device, and method, generating a clock output from a phase lock loop block via a sub-module clocking component; multiplexing the clock output through a global clock into different clock domains; clocking the data and an address or a command path by each clock domain; clocking the phase compensation FIFO by clock domain and clock phase alignment clock; generating the pointer for the phase compensation FIFO from central pointer generator block; and synchronizing the pointer of the adjacent intellectual property module with a parent intellectual property module.


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