The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2023

Filed:

Sep. 04, 2020
Applicants:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Toshiba Electronic Devices & Storage Corporation, Tokyo, JP;

Inventors:

Tatsuya Shiraishi, Nonoichi Ishikawa, JP;

Masaharu Shimabayashi, Kanazawa Ishikawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 29/401 (2013.01); H01L 29/42364 (2013.01); H01L 29/511 (2013.01); H01L 21/0217 (2013.01); H01L 21/02271 (2013.01); H01L 21/28202 (2013.01); H01L 29/16 (2013.01); H01L 29/407 (2013.01); H01L 29/518 (2013.01);
Abstract

A semiconductor device includes: a first electrode; a first semiconductor layer of first conductivity type provided on the first electrode; a second semiconductor layer of first conductivity type provided on the first semiconductor layer; a first semiconductor region of second conductivity type provided on the second semiconductor layer; a second semiconductor region of second conductivity type provided on the second semiconductor layer; a first insulating film provided in a trench between the first semiconductor region and the second semiconductor region, the trench reaching the second semiconductor layer from above the first semiconductor region and the second semiconductor region, the first insulating film containing silicon oxide; a second electrode provided in the trench, the second electrode facing the second semiconductor layer via the first insulating film, the second electrode containing polysilicon; a third electrode provided above the second electrode, the third electrode facing the first semiconductor region and the second semiconductor region via a second insulating film containing silicon oxide; a third insulating film provided between the second electrode and the third electrode, the third insulating film containing silicon nitride; a third semiconductor region of first conductivity type provided on the first semiconductor region; a fourth semiconductor region of first conductivity type provided on the second semiconductor region; an interlayer insulating film provided on the third electrode; and a fourth electrode provided on the interlayer insulating film, the fourth electrode being electrically connected to the third semiconductor region and the fourth semiconductor region.


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