The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2023

Filed:

Jan. 04, 2021
Applicant:

Anpec Electronics Corporation, Hsinchu, TW;

Inventors:

Yu-Wen Wang, Hsinchu, TW;

Jia-Hua Hong, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03G 1/00 (2006.01); G05B 19/4155 (2006.01); G01R 27/28 (2006.01); H03G 3/00 (2006.01);
U.S. Cl.
CPC ...
G05B 19/4155 (2013.01); G01R 27/28 (2013.01); H03G 1/0088 (2013.01); H03G 3/001 (2013.01); G05B 2219/34292 (2013.01);
Abstract

A signal gain determination circuit including a digital comparator, a digital controller and an arithmetic module, and a signal gain determination method are provided. A sensing integration circuit generates a first count during a first integration time according to a first sensing signal. The digital comparator compares the first count and a predetermined count to generate a comparison result. The digital controller generates a control signal for indicating a signal gain to a signal amplifier of the sensing integration circuit according to the comparison result. The signal amplifier adjusts the first sensing signal according to the signal gain to generate a second sensing signal, so that the sensing integration circuit generates a second count corresponding to the second sensing signal during a second integration time. The arithmetic module generates an output count corresponding to the first sensing signal according to the second count and the signal gain.


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