The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2023

Filed:

Aug. 26, 2019
Applicant:

Tdk Corporation, Tokyo, JP;

Inventors:

Naoki Ohta, Tokyo, JP;

Yuji Kakinuma, Tokyo, JP;

Shinji Hara, Tokyo, JP;

Susumu Aoki, Tokyo, JP;

Keita Kawamori, Tokyo, JP;

Eiji Komura, Tokyo, JP;

Assignee:

TDK CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G01J 1/44 (2006.01); H01L 27/24 (2006.01); H03F 3/45 (2006.01); G11C 13/00 (2006.01); H01L 37/02 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
G01J 1/44 (2013.01); G11C 13/004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0028 (2013.01); G11C 13/0038 (2013.01); H01L 27/2463 (2013.01); H01L 37/02 (2013.01); H01L 45/128 (2013.01); H01L 45/146 (2013.01); H03F 3/45071 (2013.01); G11C 2013/0045 (2013.01); G11C 2213/32 (2013.01); G11C 2213/77 (2013.01);
Abstract

A resistive element array circuit includes word lines, bit lines, resistive elements, a selector, a differential amplifier, and a ground terminal. The word lines are coupled to a power supply. The resistive elements are each disposed at an intersection of corresponding one of the word lines and corresponding one of the bit lines. The selector is configured to select one word line and one bit line. The differential amplifier includes a positive input terminal configured to be coupled to the selected one of the bit lines which is selected by the selector, a negative input terminal configured to be coupled to non-selected one of the bit lines which is not selected by the selector and to non-selected one of the word lines which is not selected by the selector, an output terminal being coupled to the negative input terminal. The ground terminal is coupled to the positive input terminal.


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