The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2023

Filed:

Jan. 29, 2021
Applicant:

Juniper Networks, Inc., Sunnyvale, CA (US);

Inventors:

Steve M. Wilkinson, San Mateo, CA (US);

Daniel J. Prezioso, Saugus, MA (US);

Assignee:

Juniper Networks, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 1/09 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); H05K 3/00 (2006.01); H05K 3/22 (2006.01); H05K 3/36 (2006.01); H05K 3/40 (2006.01); H05K 3/42 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H05K 3/425 (2013.01); H05K 3/22 (2013.01);
Abstract

A method may include obtaining a printed circuit board (PCB) that includes a set of vias that include a set of stub regions. The PCB may include a set of layers perpendicular to the set of vias. The set of layers may include a signal layer and a ground layer. The ground layer may be located between the set of stub regions and the signal layer. The method may include drilling to remove at least a portion of a stub region of a via of the set of vias. The method may include performing an electrical test to determine whether a sliver of conductive material is included within the via after drilling to remove the at least a portion of the stub region of the via.


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