The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2023

Filed:

Jul. 18, 2018
Applicants:

Centre National DE LA Recherche Scientifique, Paris, FR;

Institut Polytechnique DE Grenoble, Grenoble, FR;

Universite Grenoble Alpes, Saint Martin d'Heres, FR;

Inventors:

Julien Pernot, Grenoble, FR;

Nicolas Rouger, Toulouse, FR;

David Eon, Saint Martin d'Heres, FR;

Etienne Gheeraert, Coublevie, FR;

Gauthier Chicot, Fontaine, FR;

Toan Thanh Pham, Grenoble, FR;

Florin Udrea, Cambridge, GB;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7838 (2013.01); H01L 29/1602 (2013.01); H01L 29/66045 (2013.01); H01L 29/7831 (2013.01); H01L 29/7851 (2013.01);
Abstract

The invention relates to a deep depletion MIS transistor (), comprising: a source region (S) and a drain region (D) made of doped semiconductor diamond of a first conductivity type; a channel region (C) made of doped semiconductor diamond of the first conductivity type, arranged between the source region and the drain region; a drift region (DR) made of doped semiconductor diamond of the first conductivity type, arranged between the channel region and the drain region; and a conductive gate () arranged on the channel region and separated from the channel region by a dielectric layer ().


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