The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2023

Filed:

Jun. 24, 2020
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Chengdu, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Linhong Han, Beijing, CN;

Shikai Qin, Beijing, CN;

Tingliang Liu, Beijing, CN;

Youngyik Ko, Beijing, CN;

Binyan Wang, Beijing, CN;

Tiaomei Zhang, Beijing, CN;

Hao Zhang, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/32 (2006.01); G02F 1/136 (2006.01); G09G 3/3225 (2016.01); G09G 3/3266 (2016.01); G09G 3/3275 (2016.01);
U.S. Cl.
CPC ...
H01L 27/3276 (2013.01); G02F 1/136 (2013.01); G09G 3/3225 (2013.01); G09G 3/3266 (2013.01); G09G 3/3275 (2013.01);
Abstract

An array substrate is provided, including: a base substrate including a display area; a racetrack hole portion in the display area, including: a long axis; a short axis; a first hole and a second hole; a frame area surrounding the first hole and the second hole; and multiple lines in the frame area. The frame area includes a first wiring area and a second wiring area, the first wiring area includes a first conductive layer, and the multiple lines located in the first wiring area are arranged in the first conductive layer; and the second wiring area includes a second conductive layer and a third conductive layer arranged in different layers, and some of the multiple lines located in the second wiring area are arranged in the second conductive layer, and other lines of the multiple lines located in the second wiring area are arranged in the third conductive layer.


Find Patent Forward Citations

Loading…