The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2023

Filed:

Jun. 04, 2021
Applicant:

Sharp Kabushiki Kaisha, Osaka, JP;

Inventors:

Hajime Imai, Sakai, JP;

Tohru Daitoh, Sakai, JP;

Teruyuki Ueda, Sakai, JP;

Yoshihito Hara, Sakai, JP;

Masaki Maeda, Sakai, JP;

Tatsuya Kawasaki, Sakai, JP;

Yoshiharu Hirata, Sakai, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/32 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/3262 (2013.01); H01L 29/66742 (2013.01); H01L 29/7869 (2013.01); H01L 29/78618 (2013.01); H01L 2227/323 (2013.01);
Abstract

An active matrix substrate includes a first TFT and a second TFT, in which the first TFT includes a first oxide semiconductor layer and a first gate electrode arranged on a part of the first oxide semiconductor layer with a first gate insulating layer interposed therebetween, the first gate insulating layer has a layered structure including a first insulating film and a second insulating film arranged on the first insulating film, the second TFT includes a second oxide semiconductor layer having a higher mobility than the first oxide semiconductor layer and a second gate electrode arranged on a part of the second oxide semiconductor layer with a second gate insulating layer interposed therebetween, and the second gate insulating layer includes the second insulating film and does not include the first insulating film, and the second TFT further includes a lower insulating layer including the first insulating film arranged between the second oxide semiconductor layer and a substrate.


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