The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2023

Filed:

Dec. 18, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kiseok Lee, Hwaseong-si, KR;

Bong-Soo Kim, Yongin-si, KR;

Jiyoung Kim, Yongin-si, KR;

Hui-Jung Kim, Seongnam-si, KR;

Seokhan Park, Seongnam-si, KR;

Hunkook Lee, Hwaseong-si, KR;

Yoosang Hwang, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 23/528 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01); H01L 29/10 (2006.01); H01L 23/522 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10805 (2013.01); H01L 23/528 (2013.01); H01L 27/10897 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/165 (2013.01); H01L 23/5226 (2013.01); H01L 28/60 (2013.01);
Abstract

Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.


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