IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11569232 B1

PDFFull Text
Date of Patent:
Jan. 31, 2023

Filed:

Jan. 19, 2021

Semiconductor device including self-aligned gate structure and method of manufacturing the same

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Byounghak Hong, Albany, NY (US);

Seunghyun Song, Albany, NY (US);

Hwichan Jun, Albany, NY (US);

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;

Attorney:

Sughrue Mion, PLLC

Primary Examiner:

Tong-Ho Kim

Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0922 (2013.01); H01L 21/02603 (2013.01); H01L 21/28123 (2013.01); H01L 21/823807 (2013.01); H01L 21/823828 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method of manufacturing a semiconductor device having a self-aligned gate structure includes: providing at least one channel structure above at least one substrate; depositing at least one gate masking layer on the at least one channel structure so that the at least one gate masking layer is formed on top and side surfaces of the at least one channel structure and spread outward above the at least one substrate to form outer-extended portions of the at least one gate masking layer, before a gate-cut process is performed, wherein the at least one gate masking layer is self-aligned with respect to the at least one channel structure by the depositing; and removing the outer-extended portions of the at least one gate masking layer so that the at least one gate masking layer at both sides of the at least one channel structure has a same width.

Find Patent Forward Citations

Loading…