The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 2023
Filed:
Jul. 15, 2020
Applicant:
Socionext Inc., Kanagawa, JP;
Inventor:
Yoshinobu Yamagami, Yokohama, JP;
Assignee:
SOCIONEXT INC., Kanagawa, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 27/02 (2006.01); H01L 23/528 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); H01L 23/5286 (2013.01); H01L 27/0928 (2013.01); H01L 27/1104 (2013.01); H01L 29/0676 (2013.01); H01L 29/7827 (2013.01);
Abstract
Provided is a layout structure capable of reducing the parasitic capacitance between storage nodes of an SRAM cell using vertical nanowire (VNW) FETs. In the SRAM cell, a first storage node is connected to top electrodes of some transistors, and a second storage node is connected to bottom electrodes of other transistors. Accordingly, the first and second storage nodes have fewer regions adjacent to each other in a single layer.