The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2023

Filed:

May. 26, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Yonghyeok Son, Seoul, KR;

Junwoo Lee, Bucheon-si, KR;

Sungdong Cho, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/76805 (2013.01); H01L 21/76843 (2013.01); H01L 21/76895 (2013.01); H01L 27/10814 (2013.01); H01L 27/10823 (2013.01); H01L 27/10855 (2013.01); H01L 27/10876 (2013.01); H01L 27/10885 (2013.01); H01L 27/10888 (2013.01); H01L 27/10894 (2013.01); H01L 27/10897 (2013.01);
Abstract

A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.


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