The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2023

Filed:

Mar. 12, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Francisco Adolfo Cano, Sugar Land, TX (US);

Devanathan Varadarajan, Allen, TX (US);

Anthony Martin Hill, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/38 (2006.01); G11C 29/50 (2006.01); G11C 11/419 (2006.01); G11C 11/418 (2006.01); G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
G11C 29/38 (2013.01); G11C 11/412 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01); G11C 29/50004 (2013.01); G11C 2029/5004 (2013.01);
Abstract

Systems and methods of screening memory cells by modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven as compared to a nominal operating voltage on the wordline. In a write operation, the one or both of the bitline and wordline may be overdriven or underdriven as compared to a nominal operating voltage of each. A built-in self test (BIST) system for screening a memory array has bitline and wordline margin controls to modulate bitline and wordline voltage, respectively, in the memory array.


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