The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2023

Filed:

Jun. 22, 2021
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Jong Hoon Lee, Gyeonggi-do, KR;

Se Chun Park, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G11C 11/5628 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01);
Abstract

The memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit may perform a program operation on the plurality of memory cells and may perform program verify operations each including at least one verify loop corresponding to a plurality of program states programmed in the program operation. The control logic may control the peripheral circuit to perform a verify pulse apply operation and an additional verify pulse apply operation when a target verify loop count exceeds a reference count corresponding to the target program state, and may determine a failure of the program verify operation corresponding to the target program state based on results of the verify pulse apply operation and the additional verify pulse apply operation. A verify voltage of the additional verify pulse apply operation is higher than a verify voltage of the verify pulse apply operation.


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