The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2023

Filed:

Jun. 09, 2021
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Anirudh Amarnath, San Jose, CA (US);

Jongyeon Kim, Milpitas, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01); G11C 16/04 (2006.01); G11C 11/56 (2006.01); H01L 27/11582 (2017.01); H01L 27/11519 (2017.01); H01L 27/11565 (2017.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); G11C 11/5628 (2013.01); G11C 11/5671 (2013.01); H01L 27/11519 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01);
Abstract

A method of verifying the programming of a plurality of memory cells in a data storage system includes performing a setup operation including settling of bit lines associated with the subset of memory cells; performing a sensing operation including subjecting the settled bit lines to a verify voltage signal; and performing first and second latching operations identifying memory cells of the subset of memory cells having threshold voltages that meet first and second verify reference voltages, where the first and second latching operations are part of the same program verify operation with no setup time between them.


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