The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2023

Filed:

May. 12, 2017
Applicant:

Lg Electronics Inc., Seoul, KR;

Inventors:

Milan Shah, San Jose, CA (US);

Tariq Afzal, San Jose, CA (US);

Thomas Zou, San Jose, CA (US);

Assignee:

LG ELECTRONICS INC., Seoul, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 12/0875 (2016.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 12/0804 (2016.01); G06F 3/06 (2006.01); G06F 12/084 (2016.01); G06F 12/0862 (2016.01); G06F 12/0897 (2016.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1673 (2013.01); G06F 3/0658 (2013.01); G06F 12/0804 (2013.01); G06F 12/084 (2013.01); G06F 12/0862 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 13/1642 (2013.01); G06F 13/40 (2013.01); G06F 13/4234 (2013.01); G06F 15/7807 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/1041 (2013.01); G06F 2212/602 (2013.01); G06F 2212/608 (2013.01); Y02D 10/00 (2018.01);
Abstract

The present disclosure relates to a system and method for optimizing switching of a DRAM bus using LLC. An embodiment of the disclosure includes sending a first type request from a first type queue to the second memory via the memory bus if a direction setting of the memory bus is in a first direction corresponding to the first type request, decrementing a current direction credit count by a first type transaction decrement value, if the decremented current direction credit count is greater than zero, sending another first type request to the second memory via the memory bus and decrementing the current direction credit count again by the first type transaction decrement value, and if the decremented current direction credit count is zero, switching the direction setting of the memory bus to a second direction and resetting the current direction credit count to a second type initial value.


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