The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2023

Filed:

Apr. 28, 2021
Applicant:

Amazon Technologies, Inc., Seattle, WA (US);

Inventors:

Jeffrey T. Huynh, San Jose, CA (US);

Drazen Borkovic, Los Altos, CA (US);

Jindrich Zejda, Saratoga, CA (US);

Randy Renfu Huang, Morgan Hill, CA (US);

Ron Diamant, Santa Clara, CA (US);

Assignee:

Amazon Technologies, Inc., Seattle, WA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/44 (2018.01); G06F 9/38 (2018.01); G06F 9/50 (2006.01); G06N 3/04 (2006.01); G06N 3/08 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3855 (2013.01); G06F 9/5016 (2013.01); G06F 9/5027 (2013.01); G06N 3/04 (2013.01); G06N 3/08 (2013.01);
Abstract

Techniques are disclosed for reordering operations of a neural network to improve runtime efficiency. In some examples, a compiler receives a description of the neural network comprising a plurality of operations. The compiler may determine which execution engine of a plurality of execution engines is to perform each of the plurality of operations. The compiler may determine an order of performance associated with the plurality of operations. The compiler may identify a runtime inefficiency based on the order of performance and a hardware usage for each of the plurality of operations. An operation may be reordered to reduce the runtime inefficiency. Instructions may be compiled based on the plurality of operations, which include the reordered operation.


Find Patent Forward Citations

Loading…