Programmable delay-based power stabilization

Abstract

Power demands of a computing system, such as a network device and/or a component thereof, are stabilized by introducing a programmable delay into identical or substantially similar subsystems within an integrated circuit. Each subsystem reads a potentially different delay value from an associated storage, memory, or input, and waits for some time indicated by the delay value before beginning execution. For example, in a group of identical subsystems that process data concurrently, some or all of the subsystems begin processing their respective data after a different amount of delay, thus staggering their respective executions and lowering the risk of aligned edges when some or all of the subsystems concurrently step their power demands up or down. This, in turn, reduces peak power and voltage. In an embodiment, rather than being fixed at the design stage, each subsystem's delay value is programmable at some point after fabrication.