The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2023

Filed:

Jun. 22, 2020
Applicant:

Acacia Communications, Inc., Maynard, MA (US);

Inventors:

Ramesh K. Singh, Newark, CA (US);

Tarun Gupta, Santa Clara, CA (US);

Guojun Ren, San Jose, CA (US);

Richard Castell, Maidenhead, GB;

Assignee:

Acacia Communications, Inc., Maynard, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/135 (2006.01); H03K 5/15 (2006.01); H03K 5/131 (2014.01); G06F 1/10 (2006.01);
U.S. Cl.
CPC ...
H03K 5/135 (2013.01); G06F 1/10 (2013.01); H03K 5/131 (2013.01); H03K 5/1508 (2013.01);
Abstract

A method and apparatus for determining a set of cascading clock cycles, the method comprising inputting a set of phase changes of a set of clocks into a set of input circuits; wherein the set of phase changes are either falling phase changes or rising phase changes; wherein two phase changes of the set of clocks are fed into each input circuit of the set of input circuits, determining for each input circuit of the set of input circuits a duty cycle, storing the duty cycle for each input circuit of the input circuits in a set of duty cycles, calculating skew between the set of clocks using the duty cycles, and adjusting a delay to lower the skew between the set of clocks.


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