The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2023

Filed:

Dec. 19, 2019
Applicant:

Avx Corporation, Fountain Inn, SC (US);

Inventors:

Kwang Choi, Simpsonville, SC (US);

Marianne Berolini, Greenville, SC (US);

Assignee:

KYOCERA AVX Components Corporation, Fountain Inn, SC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 7/01 (2006.01); H01G 4/30 (2006.01); H01G 4/005 (2006.01); H01G 4/12 (2006.01); H01L 49/02 (2006.01); H01G 2/06 (2006.01); H05K 3/46 (2006.01); H05K 1/11 (2006.01); H03H 1/00 (2006.01);
U.S. Cl.
CPC ...
H03H 7/0115 (2013.01); H01G 2/065 (2013.01); H01G 4/005 (2013.01); H01G 4/12 (2013.01); H01G 4/30 (2013.01); H01L 28/60 (2013.01); H03H 7/01 (2013.01); H05K 1/11 (2013.01); H05K 3/4697 (2013.01); H03H 2001/0085 (2013.01); H05K 2201/10015 (2013.01); H05K 2201/10515 (2013.01);
Abstract

A multilayer electronic device may include a plurality of dielectric layers stacked in a Z-direction that is perpendicular to an X-Y plane. The device may include a first conductive layer overlying one of the plurality of dielectric layers. The multilayer electronic device may include a second conductive layer overlying another of the plurality of dielectric layers and spaced apart from the first conductive layer in the Z-direction. The second conductive layer may overlap the first conductive layer in the X-Y plane at an overlapping area to form a capacitor. The first conductive layer may have a pair of parallel edges at a boundary of the overlapping area and an offset edge within the overlapping area that is parallel with the pair of parallel edges. An offset distance between the offset edge and at least one of the pair of parallel edges may be less than about 500 microns.


Find Patent Forward Citations

Loading…