The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2023

Filed:

Aug. 24, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Julian Becker, Freising, DE;

Christian Harder, Freising, DE;

Eduardas Jodka, Freising, DE;

Stefan Dietrich, Oberding, DE;

Puneet Sareen, Freising, DE;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02M 1/08 (2006.01); H02M 3/156 (2006.01); G05F 1/46 (2006.01); H02M 3/158 (2006.01); H03K 5/24 (2006.01); G05F 3/26 (2006.01); G01R 19/165 (2006.01); H02M 1/14 (2006.01); H02M 1/00 (2006.01); G05F 1/575 (2006.01);
U.S. Cl.
CPC ...
H02M 3/1584 (2013.01); G01R 19/16528 (2013.01); G05F 3/262 (2013.01); H02M 1/14 (2013.01); H03K 5/24 (2013.01); G05F 1/462 (2013.01); G05F 1/575 (2013.01); H02M 1/0009 (2021.05); H02M 1/0012 (2021.05); H02M 1/0025 (2021.05); H02M 1/08 (2013.01); H02M 3/156 (2013.01);
Abstract

A converter operable to convert an input voltage at an input node to an output voltage at an output node coupled to a load by switching on and off a transistor at a switching frequency, the converter comprising: an error amplifier circuit having a first input coupled to a reference voltage, a second input coupled to the output node through a resistive divider, a first output operable to output a control current and a second output operable to output a current equivalent to the control current; a peak current comparator circuit having a first input coupled to the second output of the error amplifier circuit, a second input and an output, the second input is coupled to the input node through an inductor; an off-time timer circuit having an input coupled to the first output of the error amplifier circuit and an output, the off-time timer circuit operable to set the switching frequency based on the control current; and a control circuit having a first input coupled to the output of the peak current comparator circuit, a second input coupled to the output of the off-time timer circuit and an output coupled to a control terminal of the transistor.


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