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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11563126 B1

PDFFull Text
Date of Patent:
Jan. 24, 2023

Filed:

Jun. 15, 2021

Method of manufacturing thin film transistor and display device including polishing capping layer coplanar with active layer

Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Kohei Ebisuno, Yongin-si, KR;

Sungjun Kim, Yongin-si, KR;

Donghyun Son, Yongin-si, KR;

Jaesoo Jung, Yongin-si, KR;

Sunghoon Moon, Yongin-si, KR;

Jingoo Jung, Yongin-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Yongin-si, KR;

Attorney:

F. Chau & Associates, LLC

Primary Examiner:

Matthew E Gordon

Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/32 (2006.01); H01L 27/12 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78696 (2013.01); H01L 21/02164 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02672 (2013.01); H01L 21/02675 (2013.01); H01L 21/30625 (2013.01); H01L 27/1222 (2013.01); H01L 27/1281 (2013.01); H01L 27/3262 (2013.01); H01L 29/66757 (2013.01); H01L 29/78675 (2013.01); H01L 2227/323 (2013.01);
Abstract

A thin film transistor includes an active layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, a capping layer filling a thickness difference between the first portion and the second portion and arranged on the first portion, a gate insulating layer arranged on the capping layer, a gate electrode on the active layer, wherein the gate insulating layer and the capping layer are disposed between the gate electrode and the active layer, and a source electrode and a drain electrode connected to the active layer.

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