The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2023

Filed:

Sep. 10, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seojin Jeong, Incheon, KR;

Jinyeong Joe, Suwon-si, KR;

Seokhoon Kim, Suwon-si, KR;

Jeongho Yoo, Seongnam-si, KR;

Seung Hun Lee, Hwaseong-si, KR;

Sihyung Lee, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/82 (2006.01); H01L 21/76 (2006.01); H01L 29/16 (2006.01); H01L 29/10 (2006.01); H01L 29/04 (2006.01); H01L 29/167 (2006.01); H01L 29/36 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 21/8238 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1604 (2013.01); H01L 21/76224 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 27/0924 (2013.01); H01L 29/04 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 29/167 (2013.01); H01L 29/36 (2013.01); H01L 29/66636 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02636 (2013.01); H01L 21/823864 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01);
Abstract

A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width.


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