The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2023

Filed:

Jun. 29, 2020
Applicants:

Ordos Yuansheng Optoelectronics Co., Ltd., Inner Mongolia, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Shuai Han, Beijing, CN;

Jingyi Xu, Beijing, CN;

Xin Zhao, Beijing, CN;

Wulijibaier Tang, Beijing, CN;

Yanwei Ren, Beijing, CN;

Yanan Yu, Beijing, CN;

Yuelin Wang, Beijing, CN;

Guolei Zhi, Beijing, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 23/00 (2006.01); G02F 1/136 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); G02F 1/136 (2013.01); H01L 24/13 (2013.01); H01L 24/14 (2013.01); H01L 27/1259 (2013.01); H01L 2224/13012 (2013.01); H01L 2224/13562 (2013.01); H01L 2224/14155 (2013.01);
Abstract

The present disclosure provides an array substrate and a fabrication method thereof, a display panel and a display module. The array substrate has a display region and a bonding region for bonding with a circuit board, and including: a data line and a gate line in the display region; and a bump unit in the bonding region. The bump unit includes: a gate line bump layer, which is in a same layer and made of a same material as the gate line, is connected to the data line, and includes a main body portion and a plurality of hollowed-out portions in the main body portion; and a data line bump layer, which is in a same layer and made of a same material as the data line, and covers the main body portion and the plurality of hollowed-out portions of the gate line bump layer.


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