The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 2023
Filed:
Jun. 09, 2021
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventors:
Sung-Lae Oh, Chungcheongbuk-do, KR;
Dong-Hyuk Kim, Seoul, KR;
Tae-Sung Park, Gyeonggi-do, KR;
Soo-Nam Jung, Seoul, KR;
Chang-Woon Choi, Seoul, KR;
Assignee:
SK hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11573 (2017.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/022 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 23/528 (2013.01); H01L 27/11573 (2013.01);
Abstract
A semiconductor memory device includes a stacked structure including a plurality of conductive layers and a plurality of interlayer insulating layers, which are alternately stacked on a substrate; stepped grooves provided in the stacked structure, the stepped grooves having different depths from each other; and an opening portion penetrating the stacked structure to contact the substrate and having steps on sidewalls, the steps having heights corresponding to depth differences between stepped grooves.