The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2023

Filed:

May. 21, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jin Woo Kim, Hwaseong-si, KR;

Choelhwyi Bae, Hwaseong-si, KR;

Yang Gyeom Kim, Hwaseong-si, KR;

Sung Eun Kim, Hwaseong-si, KR;

Sang Woo Pae, Hwaseong-si, KR;

Hyun Chui Sagong, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 27/11 (2006.01); H01L 29/40 (2006.01); H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 21/765 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0922 (2013.01); H01L 21/28088 (2013.01); H01L 21/765 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 27/0924 (2013.01); H01L 27/1104 (2013.01); H01L 29/402 (2013.01); H01L 29/4966 (2013.01);
Abstract

A semiconductor device includes a first fin that protrudes from a substrate and extends in a first direction, a second fin that protrudes from the substrate and extends in the first direction, the first fin and the second fin being spaced apart, a gate line including a dummy gate electrode and a gate electrode, the dummy gate electrode at least partially covering the first fin, the gate electrode at least partially covering the second fin, the dummy gate electrode including different materials from the gate electrode, the gate line covering the first fin and the second fin, the gate line extending in a second direction different from the first direction, and a gate dielectric layer between the gate electrode and the second fin.


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