The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2023

Filed:

Oct. 14, 2020
Applicant:

Hrl Laboratories, Llc, Malibu, CA (US);

Inventors:

Peter Brewer, Westlake Village, CA (US);

Aurelio Lopez, Thousand Oaks, CA (US);

Partia Naghibi-Mahmoudabadi, Canoga Park, CA (US);

Tahir Hussain, Calabasas, CA (US);

Assignee:

HRL LABORATORIES, LLC, Malibu, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 25/50 (2013.01); H01L 2224/10135 (2013.01); H01L 2224/1607 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/81143 (2013.01); H01L 2224/81385 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06593 (2013.01);
Abstract

A method and apparatus for laterally urging two semiconductor chips, dies or wafers into an improved state of registration with each other, the method and apparatus employing microstructures comprising: a first microstructure disposed on a first major surface of a first one of said two semiconductor chips, dies or wafers, wherein the first microstructure includes a sidewall which is tapered thereby disposing it at an acute angle compared to a perpendicular of said first major surface, and a second microstructure disposed on a first surface of a second one of said two semiconductor chips, dies or wafers, wherein the shape of the second microstructure is complementary to, and mates with or contacts, in use, the first microstructure, the second microstructure including a surface which contacts said sidewall when the first and second microstructures are mated or being mated, the sidewall of the first microstructure and the surface of the second microstructure imparting a lateral force for urging the two semiconductor chips, dies or wafers into said improved state of registration.


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