The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2023

Filed:

Jun. 28, 2018
Applicant:

Amazon Technologies, Inc., Seattle, WA (US);

Inventors:

Richard John Heaton, San Jose, CA (US);

Randy Renfu Huang, Morgan Hill, CA (US);

Drazen Borkovic, Los Altos, CA (US);

Jindrich Zejda, Saratoga, CA (US);

Assignee:

Amazon Technologies, Inc., Seattle, WA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 9/54 (2006.01); G06F 9/38 (2018.01); G06N 3/04 (2006.01);
U.S. Cl.
CPC ...
G06F 9/5016 (2013.01); G06F 9/3836 (2013.01); G06F 9/50 (2013.01); G06F 9/5005 (2013.01); G06F 9/5022 (2013.01); G06F 9/5061 (2013.01); G06F 9/5077 (2013.01); G06F 9/544 (2013.01); G06N 3/0454 (2013.01);
Abstract

Techniques for operating a computing system to perform neural network operations are disclosed. In one example, a method comprises receiving a neural network model, determining a sequence of neural network operations based on data dependency in the neural network model, and determining a set of instructions to map the sequence of neural network operations to the processing resources of the neural network processor. The method further comprises determining, based on a set of memory access operations included in the set of instructions, a first set of memory references associated with a first location of an external memory to store the input data and a second set of memory references associated with a second location of the external memory to store the output data, and generating an instruction file including the set of instructions, the first set of memory references and the second set of memory references.


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