The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2023

Filed:

Dec. 01, 2020
Applicant:

Ciena Corporation, Hanover, MD (US);

Inventors:

Mahdi Parvizi, Kanata, CA;

Sadok Aouini, Gatineau, CA;

Naim Ben-Hamida, Nepean, CA;

Yuriy Greshishchev, Ottawa, CA;

Douglas Stuart McPherson, Ottawa, CA;

Assignee:

Ciena Corporation, Hanover, MD (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/08 (2006.01); G06F 1/324 (2019.01); G06F 7/68 (2006.01); G06F 1/10 (2006.01); H03B 19/10 (2006.01); H03M 1/66 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); G06F 1/10 (2013.01); G06F 1/324 (2013.01); G06F 7/68 (2013.01); H03B 19/10 (2013.01); H03M 1/66 (2013.01);
Abstract

Described are apparatus and methods for low power frequency clock generation and distribution. A device includes a low power generation and distribution circuit configured to generate and distribute a differential 1/N sampling frequency (F)(F/N) clock, wherein N is larger or equal to 2, and a differential frequency doubler configured to generate a single-ended multiplied frequency clock from the differential F/N frequency clock, and convert the single-ended multiplied frequency clock to a differential multiplied frequency clock for use by one or more data processing channels.


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