The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2023

Filed:

Apr. 07, 2020
Applicant:

Cisco Technology, Inc., San Jose, CA (US);

Inventors:

Eric Voit, Bethesda, MD (US);

Srinivas Vundru, Cary, NC (US);

Peter Panburana, Morrisville, NC (US);

David Wayne Mills, Raleigh, NC (US);

Pradeep Kumar Kathail, Los Altos, CA (US);

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); H04L 9/32 (2006.01); H04L 9/30 (2006.01); H04L 9/08 (2006.01);
U.S. Cl.
CPC ...
H04L 9/3234 (2013.01); H04L 9/0897 (2013.01); H04L 9/30 (2013.01); H04L 9/3247 (2013.01); H04L 9/3297 (2013.01);
Abstract

The present technology discloses methods and systems for receiving a security profile request from an integrity verifier, the request including a nonce; requesting, from a trusted platform module, a new nonce, wherein the new nonce is generated at least in part by the nonce and a current timestamp from a clock in the trusted platform module; receiving, from the trusted platform module, the new nonce; requesting, from a cryptoprocessor, a set of platform configuration registers; receiving, from the cryptoprocessor, the set of platform configuration registers; and sending a response to the integrity verifier, the response including the new nonce and the set of platform configuration registers to verify a security status of the trusted platform module and the cryptoprocessor.


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