The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2023

Filed:

Dec. 06, 2019
Applicant:

Hkc Corporation Limited, Guangdong, CN;

Inventors:

Qionghua Mo, Guangdong, CN;

En-tsung Cho, Guangdong, CN;

Assignee:

HKC CORPORATION LIMITED, Guangdong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1222 (2013.01); H01L 29/42364 (2013.01); H01L 29/66765 (2013.01); H01L 29/78669 (2013.01);
Abstract

Disclosed are a method and a device for manufacturing an array substrate, and an array substrate. The method includes: depositing and forming a gate insulation layer on a pre-formed base substrate and a pre-formed gate, the gate insulation layer covering the pre-formed gate; depositing and forming an amorphous silicon layer, a doped amorphous silicon layer including at least three doped layers, and a metal layer on the gate insulation layer in sequence, doping concentrations of the at least three doped layers of the doped amorphous silicon layer increasing from bottom to top; etching patterns of the amorphous silicon layer, the doped amorphous silicon layer and the metal layer to form the array substrate.


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