The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 17, 2023
Filed:
Oct. 31, 2019
Applicant:
Nxp B.v., Eindhoven, NL;
Inventors:
Leo van Gemert, Nijmegen, NL;
Peter Joseph Hubert Drummen, Someren, NL;
Assignee:
NXP B.V., Eindhoven, NL;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 21/48 (2006.01); H01L 23/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/563 (2013.01); H01L 21/4853 (2013.01); H01L 23/3157 (2013.01); H01L 23/552 (2013.01); H01L 23/66 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2224/16157 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/3025 (2013.01);
Abstract
A method of forming an assembly is provided. The method includes attaching a packaged semiconductor device to a substrate. An isolation structure is formed and located between the packaged semiconductor device and the substrate. An underfill material is dispensed between the packaged semiconductor device and the substrate. The isolation structure prevents the underfill material from contacting a first conductive connection formed between the packaged semiconductor device and the substrate.