The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2023

Filed:

Aug. 16, 2019
Applicant:

Nxp B.v., Eindhoven, NL;

Inventor:

Jan-Peter Schat, Hamburg, DE;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/42 (2006.01); G11C 29/52 (2006.01); G06F 11/10 (2006.01); G11C 11/4096 (2006.01); G11C 29/56 (2006.01); G11C 29/44 (2006.01); G11C 29/10 (2006.01); G11C 29/12 (2006.01);
U.S. Cl.
CPC ...
G11C 29/42 (2013.01); G06F 11/1068 (2013.01); G11C 29/52 (2013.01); G11C 11/4096 (2013.01); G11C 29/10 (2013.01); G11C 29/12 (2013.01); G11C 29/44 (2013.01); G11C 2029/5602 (2013.01);
Abstract

Embodiments combine error correction code (ECC) and transparent memory built-in self-test (TMBIST) for memory fault detection and correction. An ECC encoder receives input data and provides ECC data for data words stored in memory. Input XOR circuits receive the input data and output XOR'ed data as payload data for the data words. Output XOR circuits receive the payload data and output XOR'ed data. An ECC decoder receives the ECC data and the XOR'ed output data and generates error messages. Either test data from a controller running a TMBIST process or application data from a processor executing an application is selected as the input data. Either test address/control signals from the controller or application address/control signals from the processor are selected for memory access. During active operation of the application, memory access is provided to the processor and the controller, and the memory is tested during the active operation.


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