The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2023

Filed:

Sep. 01, 2020
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventor:

Sridhar Prudvi Raj Gunda, Karnataka, IN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 16/10 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0611 (2013.01); G06F 3/0644 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 11/5628 (2013.01); G11C 11/5671 (2013.01); G11C 16/10 (2013.01);
Abstract

Techniques for reducing write amplification in solid state storage are disclosed. A storage device includes single-level cell (SLC) and multi-level cell (MLCs) portions. A controller may allocate for storage in the SLC portions a sequential closed block pool for sequential data and a random closed block pool for random data. Responsive to certain conditions, the controller may relocate the sequential and random data from the respective sequential and random closed block pools to the MLC portions. The sequential data are relocated prior to the random data. Delaying relocation of random data reduces valid count at the relocation time, reducing write amplification and improving random reads.


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