The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2023

Filed:

Mar. 09, 2020
Applicants:

Ordos Yuansheng Optoelectronics Co., Ltd., Inner Mongolia, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Weilin Lai, Beijing, CN;

Yucheng Chan, Beijing, CN;

Jianbang Huang, Beijing, CN;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 27/32 (2006.01); H01L 29/66 (2006.01); H01L 51/56 (2006.01); H01L 29/786 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 21/8234 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/768 (2006.01); H01L 51/52 (2006.01);
U.S. Cl.
CPC ...
H01L 27/3262 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/8234 (2013.01); H01L 21/84 (2013.01); H01L 27/12 (2013.01); H01L 27/3246 (2013.01); H01L 27/3248 (2013.01); H01L 27/3258 (2013.01); H01L 27/3276 (2013.01); H01L 29/66772 (2013.01); H01L 29/78654 (2013.01); H01L 51/5218 (2013.01); H01L 51/5234 (2013.01); H01L 51/56 (2013.01); H01L 27/124 (2013.01); H01L 27/1222 (2013.01); H01L 27/1248 (2013.01); H01L 27/1262 (2013.01); H01L 2251/5315 (2013.01);
Abstract

An array substrate, its manufacturing method, and a display apparatus are provided. The array substrate having a substrate, includes: a monocrystalline silicon substrate employed as the substrate including a central display area, a first peripheral area, and a second peripheral area; substrate circuits integrated with a scan drive circuit in the first peripheral area, a data drive circuit in the second peripheral area, and a plurality of pixel circuits in the central display area; a plurality of scan lines in the central display area and coupled to the scan drive circuit; and a plurality of data lines in the central display area and coupled to the data drive circuit. The scan drive circuit, the data drive circuit, and the plurality of pixel circuits include a plurality of transistors, each of which has an active region inside the monocrystalline silicon layer.


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