The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2023

Filed:

Dec. 30, 2019
Applicant:

Delta Electronics (Shanghai) Co., Ltd, Shanghai, CN;

Inventors:

Zengsheng Wang, Shanghai, CN;

Xuetao Guo, Shanghai, CN;

Kai Lu, Shanghai, CN;

Hui Li, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/24 (2013.01); H01L 21/56 (2013.01); H01L 24/09 (2013.01); H01L 24/25 (2013.01); H01L 24/82 (2013.01); H01L 2224/0903 (2013.01); H01L 2224/0916 (2013.01); H01L 2224/09151 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/24155 (2013.01); H01L 2224/24175 (2013.01); H01L 2224/24991 (2013.01); H01L 2224/2518 (2013.01); H01L 2224/8213 (2013.01);
Abstract

The present disclosure relates to an embedded packaging module comprising a first semiconductor device, a first packaging layer and a first wiring layer, the first semiconductor device having a first and a second face, at least two positioning bulges and at least one bonding pad being provided on the first face of the first semiconductor device; the first packaging layer being formed on both the first face and a surface adjacent to the first face, the positioning bulges being positioned in the first packaging layer, at least one first via hole being provided in the first packaging layer, the bottom of the first via hole being positioned in the bonding pad and contacting with the bonding pad; the first wiring layer being positioned on the side of the first packaging layer away from the first semiconductor device and being electrically connected with the bonding pad through the first via hole.


Find Patent Forward Citations

Loading…