The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2023

Filed:

May. 06, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sunggi Ahn, Jinju-si, KR;

Yesin Ryu, Seoul, KR;

Jun Jin Kong, Yongin-si, KR;

Eunae Lee, Hwaseong-si, KR;

Jihyun Choi, Daegu, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/14 (2006.01); G11C 29/42 (2006.01); G11C 29/46 (2006.01); G11C 29/52 (2006.01); G11C 29/12 (2006.01);
U.S. Cl.
CPC ...
G11C 29/42 (2013.01); G11C 29/14 (2013.01); G11C 29/46 (2013.01); G11C 29/52 (2013.01); G11C 2029/1202 (2013.01); G11C 2029/1204 (2013.01);
Abstract

A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit and a control logic circuit to control the ECC circuit. The memory cell array includes memory cells and a normal cell region and a parity cell region The ECC circuit, in a normal mode, receives a main data, performs an ECC encoding on the main data to generate a parity data and stores the main data and the parity data in the normal cell region and the parity cell region. The ECC circuit, in a test mode, receives a test data including at least one error bit, stores the test data in one of the normal cell region and the parity cell region and performs an ECC decoding on the test data and one of the main data and the parity data to provide a decoding result data to an external device.


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