The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2023

Filed:

Nov. 06, 2020
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Rajdeep Gautam, Yokohama, JP;

Akira Okada, Yokohama, JP;

Assignee:

SanDisk Technologies LLC, Addison, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/30 (2006.01); G11C 16/34 (2006.01); G11C 16/26 (2006.01); G11C 16/20 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G11C 16/20 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01);
Abstract

A method for programming a target memory cell in a memory array of a non-volatile memory system, the method comprising defining a default read biasing voltage value and a default verify biasing voltage value for each program state of a target memory cell of a memory structure, determining a location of a target memory cell within the memory structure and, based upon the determined location of the target memory cell, applying a first incremental offset voltage to the default read biasing voltage value with respect to each program state, and applying a second incremental offset voltage to the default verify biasing voltage value with respect to each program state.


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