The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2023

Filed:

May. 20, 2020
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Hideki Uochi, Kanagawa, JP;

Koichiro Kamata, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 13/00 (2006.01); G11C 11/404 (2006.01); H01L 29/24 (2006.01); H01L 27/115 (2017.01); H01L 29/16 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0007 (2013.01); G11C 11/404 (2013.01); G11C 13/003 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); H01L 27/115 (2013.01); H01L 29/16 (2013.01); H01L 29/24 (2013.01); H01L 29/247 (2013.01); H01L 29/49 (2013.01); G11C 2013/0045 (2013.01); G11C 2013/0078 (2013.01); G11C 2213/53 (2013.01);
Abstract

Disclosed is a semiconductor device having a memory cell which comprises a transistor having a control gate and a storage gate. The storage gate comprises an oxide semiconductor and is able to be a conductor and an insulator depending on the potential of the storage gate and the potential of the control gate. Data is written by setting the potential of the control gate to allow the storage gate to be a conductor, supplying a potential of data to be stored to the storage gate, and setting the potential of the control gate to allow the storage gate to be an insulator. Data is read by supplying a potential for reading to a read signal line connected to one of a source and a drain of the transistor and detecting the change in potential of a bit line connected to the other of the source and the drain.


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