The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2023

Filed:

Jan. 29, 2021
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Avishek Biswas, Dallas, TX (US);

Mahesh Madhukar Mehendale, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 11/4094 (2006.01); G11C 11/4097 (2006.01); G11C 11/4074 (2006.01); G11C 11/4099 (2006.01); G06F 7/52 (2006.01); G11C 11/54 (2006.01); G11C 7/10 (2006.01); G06N 3/063 (2006.01); G06N 3/04 (2006.01); G11C 7/16 (2006.01); G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4094 (2013.01); G06F 7/52 (2013.01); G06N 3/0454 (2013.01); G06N 3/0635 (2013.01); G11C 5/06 (2013.01); G11C 7/1006 (2013.01); G11C 7/16 (2013.01); G11C 11/4074 (2013.01); G11C 11/4097 (2013.01); G11C 11/4099 (2013.01); G11C 11/54 (2013.01); G11C 11/412 (2013.01);
Abstract

A device includes a comparator to provide an indication of a difference between Vp on a first terminal coupled to a top plate of each of a first group of differential capacitors, and Vn on a second terminal coupled to a top plate of each of a second group of differential capacitors. The device includes a control circuit coupled to the comparator. The control circuit is to receive a first indication of a difference between Vp and Vn; responsive to the first indication, cause a first driver to provide a reference voltage to bottom plates of one of the first and second groups, and cause a second driver to provide a ground voltage to bottom plates of the other of the first and second groups; receive a second indication of a difference between Vp and Vn; and provide a digital value responsive to the first indication and the second indication.


Find Patent Forward Citations

Quick Actions:

Biswas, Avishek. (2023). Computation in-memory architecture for analog-to-digital conversion (U.S. Patent No. 11551745). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11551745

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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