The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2023

Filed:

Aug. 31, 2020
Applicant:

Siemens Industry Software Inc., Plano, TX (US);

Inventors:

Vipul Kulshrestha, Burlington, MA (US);

Amit Agrawal, Waltham, MA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/337 (2020.01); G06F 30/327 (2020.01); G06F 30/31 (2020.01); G06F 30/32 (2020.01); G06F 30/33 (2020.01); G06F 117/08 (2020.01);
U.S. Cl.
CPC ...
G06F 30/337 (2020.01); G06F 30/31 (2020.01); G06F 30/32 (2020.01); G06F 30/327 (2020.01); G06F 30/33 (2020.01); G06F 30/30 (2020.01); G06F 2117/08 (2020.01);
Abstract

This application discloses a distributed computing system implementing multiple participating processes to separately compile different portions of a circuit design describing an electronic device over multiple phases. The distributed computing system can implement a management process to utilize a synchronization protocol to identify operational states of the participating processes during compilation of the different portions of the circuit design, maintain the operational states of the participating processes, and separately determine when the participating processes have completed compilation of the circuit design portions for one of the phases based on the operational states of the participating processes. The management process can determine to have the participating processes synchronously transition to another one of the phases or that the participating processes have compiled the circuit design into a compiled design corresponding to the circuit design, and deploy the compiled design in an emulator for verification of a functionality of the electronic device.


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