The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2023

Filed:

Mar. 02, 2021
Applicants:

Ati Technologies Ulc, Markham, CA;

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Philip Ng, Markham, CA;

Nippon Raval, Markham, CA;

BuHeng Xu, Beijing, CN;

Rostislav S. Dobrin, Markham, CA;

Shawn Han, Suzhou, CN;

Assignees:

ATI TECHNOLOGIES ULC, Markham, CA;

ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/0831 (2016.01); G06F 12/02 (2006.01); G06F 13/24 (2006.01); G06F 13/16 (2006.01); G06F 12/1009 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0835 (2013.01); G06F 12/0238 (2013.01); G06F 12/1009 (2013.01); G06F 13/1668 (2013.01); G06F 13/24 (2013.01);
Abstract

Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One system includes a host processor; a memory; a data fabric coupled to the host processor and to the memory; a first input/output memory manage unit (IOMMU) and a second IOMMU, each of the first and second IOMMUs coupled to the data fabric; a first root port and a second root port, each of the first and second root ports coupled to a corresponding IOMMU of the first and second IOMMUs; and a first peripheral component endpoint and a second peripheral component endpoint, each of the first and second peripheral component endpoints coupled to a corresponding root port of the first and second root ports, wherein each of the first and second root ports comprises hardware control logic operative to: synchronize the first and second root ports.


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