The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2023

Filed:

Sep. 30, 2019
Applicant:

Emc Ip Holding Company Llc, Hopkinton, MA (US);

Inventors:

Bing Liu, Tianjin, CN;

Tao Chen, Beijing, CN;

Wei Lin, Beijing, CN;

Yong Zou, San Jose, CA (US);

Assignee:

EMC IP HOLDING COMPANY LLC, Hopkinton, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 9/08 (2006.01); H04L 9/30 (2006.01); G06F 16/174 (2019.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); H04L 9/34 (2006.01);
U.S. Cl.
CPC ...
H04L 9/0825 (2013.01); G06F 9/30007 (2013.01); G06F 9/3877 (2013.01); G06F 16/1744 (2019.01); H04L 9/30 (2013.01); H04L 9/34 (2013.01);
Abstract

A method, apparatus, and system for assigning the execution of a cryptography and/or compression operation on a data segment to either a central processing unit (CPU) or a hardware accelerator is disclosed. In particular, a data segment on which a cryptography and/or compression operation is to be executed is received. Status information relating to a CPU and a hardware accelerator is determined. Whether the operation is to be executed on the CPU or on the hardware accelerator is determined based at least in part on the status information. In response to determining that the operation is to be executed on the CPU, the data segment is forwarded to the CPU for execution of the operation. On the other hand, in response to determining that the operation is to be executed on the hardware accelerator, the data segment is forwarded to the hardware accelerator for execution of the operation.


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