The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2023

Filed:

Jul. 31, 2019
Applicant:

Marvell Asia Pte, Ltd., Singapore, SG;

Inventors:

Thucydides Xanthopoulos, Watertown, MA (US);

Nitin Mohan, Northborough, MA (US);

Assignee:

MARVELL ASIA PTE, LTD., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/08 (2006.01); H03L 7/081 (2006.01); G06F 1/324 (2019.01); G06F 1/10 (2006.01); H03L 7/07 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0816 (2013.01); G06F 1/10 (2013.01); G06F 1/324 (2013.01); H03L 7/07 (2013.01); H03L 7/0818 (2013.01);
Abstract

A delay-locked loop (DLL) and corresponding method improve frequency of a chip. The DLL comprises a first programmable delay element configured to output a first clock, a second programmable delay element configured to output a second clock a phase detector. The phase detector includes a first clock input and a second clock input. The first and second programmable delay elements are further configured, in combination, to introduce a controllable skew between the first and second clocks. The DLL is configured to input the first and second clocks to the first and second clock inputs of the phase detector, respectively. The controllable skew is configured to improve the frequency of the chip.


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