The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2023
Filed:
Dec. 06, 2021
Rogers Corporation, Chandler, AZ (US);
Stephen O'Connor, West Roxbury, MA (US);
Gianni Taraschi, Arlington, MA (US);
Christopher Brown, Natick, MA (US);
Kristi Pance, Auburndale, MA (US);
Karl E. Sprentall, Medford, MA (US);
Bruce Fitts, Phoenix, AZ (US);
Dirk Baars, Chandler, AZ (US);
William Blasius, Charlton, MA (US);
Murali Sethumadhavan, Acton, MA (US);
Roshin Rose George, Burlington, MA (US);
Michael S. White, Pomfret Center, CT (US);
Michael Lunt, Scotland, CT (US);
Sam Henson, Scottsdale, AZ (US);
John Dobrick, Rockwall, TX (US);
ROGERS CORPORATION, Chandler, AZ (US);
Abstract
An electromagnetic, EM, device, includes: a substrate having a dielectric layer and a first conductive layer at a first side of the substrate, the substrate having a via that extends at least partially through the substrate from the first side toward an opposing second side of the substrate; at least one dielectric structure having at least one non-gaseous dielectric material that forms a first dielectric portion that extends outward from the first side of the substrate, the first dielectric portion having a first average dielectric constant, the at least one dielectric structure further having a second dielectric portion that is contiguous with the first dielectric portion; wherein the second dielectric portion extends into the via of the substrate, the via having a mechanical interlock surface; and wherein the at least one dielectric structure includes a mechanical interlock between the second dielectric portion and the mechanical interlock surface of the via of the substrate.