The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2023

Filed:

Apr. 19, 2021
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventor:

Chih-Tsung Wu, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 27/088 (2006.01); H01L 29/786 (2006.01); H01L 21/8234 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42392 (2013.01); H01L 21/823437 (2013.01); H01L 21/823475 (2013.01); H01L 23/535 (2013.01); H01L 23/53238 (2013.01); H01L 27/088 (2013.01); H01L 29/78696 (2013.01);
Abstract

The present disclosure provides a semiconductor device with an air gap between gate-all-around (GAA) transistors and a method for forming the semiconductor device. The semiconductor device includes a first gate stack and a second gate stack disposed over a semiconductor substrate. At least one of the first gate stack and the second gate stack includes a plurality of gate layers, and the first gate stack and the second gate stack have an air gap therebetween. The semiconductor device also includes a first gate structure and a second gate structure disposed over the first gate stack and the second gate stack, respectively, and a first dielectric layer surrounds lower sidewalls of the first gate structure and lower sidewalls of the second gate structure. A width of the first gate structure is greater than a width of the first plug.


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